library verilog;
use verilog.vl_types.all;
entity modulo is
    port(
        clk             : in     vl_logic;
        dado_modulo     : in     vl_logic_vector(15 downto 0);
        saida_modulo    : out    vl_logic_vector(15 downto 0);
        dado_ok         : out    vl_logic
    );
end modulo;
